The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jul. 13, 2012
Applicants:

Jung-sik Kim, Seoul, KR;

Cheol Kim, Seoul, KR;

Sang-ho Shin, Yongin-si, KR;

Jung-bae Lee, Seongnam-si, KR;

Chan-yong Lee, Suwon-si, KR;

Sung-min Yim, Suwon-si, KR;

Tae-seong Jang, Suji-gu, KR;

Joo-sun Choi, Yongin-si, KR;

Inventors:

Jung-sik Kim, Seoul, KR;

Cheol Kim, Seoul, KR;

Sang-ho Shin, Yongin-si, KR;

Jung-bae Lee, Seongnam-si, KR;

Chan-yong Lee, Suwon-si, KR;

Sung-min Yim, Suwon-si, KR;

Tae-seong Jang, Suji-gu, KR;

Joo-sun Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/08 (2006.01); G11C 7/00 (2006.01); G11C 29/50 (2006.01); G11C 11/406 (2006.01); G11C 5/04 (2006.01); G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50016 (2013.01); G11C 11/406 (2013.01); G11C 11/40615 (2013.01); G11C 5/04 (2013.01); G11C 11/40 (2013.01); G11C 11/40622 (2013.01);
Abstract

A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.


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