Apparatus and a method for erasing data stored in a memory device

Abstract

The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage of data remanence effects, by ensuring that stored data is overwritten in an efficient, and clock independent, manner, triggered by assertion of an erase signal generated if a pulse-based control signal does not take it is expected form.