The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Oct. 05, 2007
Applicants:
Sadik C. Esener, Solana Beach, CA (US);
Haijiang Zhang, Milpitas, CA (US);
Pengyue Wen, La Jolla, CA (US);
Matthias Gross, San Diego, CA (US);
Inventors:
Sadik C. Esener, Solana Beach, CA (US);
Haijiang Zhang, Milpitas, CA (US);
Pengyue Wen, La Jolla, CA (US);
Matthias Gross, San Diego, CA (US);
Assignee:
The Regents of the University of California, Oakland, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/00 (2006.01); G02F 3/02 (2006.01); H04B 10/291 (2013.01); H01S 5/04 (2006.01); H01S 5/06 (2006.01); H01S 5/183 (2006.01); H01S 5/42 (2006.01); H01S 5/50 (2006.01);
U.S. Cl.
CPC ...
G02F 3/02 (2013.01); H01S 5/041 (2013.01); H01S 5/0607 (2013.01); H01S 5/18308 (2013.01); H01S 5/423 (2013.01); H01S 5/50 (2013.01); H04B 10/2914 (2013.01);
Abstract
Vertical cavity semiconductor optical amplifiers for various photonic devices including all optical logic gate devices and oscillators, where such devices can be implemented to achieve various advantages, including Boolean inversion at high speeds, low power, workable noise margins for cascadability because of input output isolation, and easy of integration in large arrays.