The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Jan. 25, 2010
Applicants:

Michael Yu Tak Young, Cupertino, CA (US);

Scott Jong Ho Limb, Palo Alto, CA (US);

William S. Wong, San Carlos, CA (US);

Robert A. Street, Palo Alto, CA (US);

Inventors:

Michael Yu Tak Young, Cupertino, CA (US);

Scott Jong Ho Limb, Palo Alto, CA (US);

William S. Wong, San Carlos, CA (US);

Robert A. Street, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/14 (2006.01); G11C 29/02 (2006.01); G01R 31/28 (2006.01); H01L 21/66 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/025 (2013.01); G01R 31/2853 (2013.01); G11C 2029/0403 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01);
Abstract

A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.


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