The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Mar. 06, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Young K. Song, San Diego, CA (US);

Yunseo Park, San Diego, CA (US);

Xiaonan Zhang, San Diego, CA (US);

Ryan D. Lane, San Diego, CA (US);

Babak Nejati, San Diego, CA (US);

Aristotele Hadjichristos, San Diego, CA (US);

Xiaoming Chen, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 25/11 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); H01L 24/81 (2013.01); H01L 23/645 (2013.01); H01L 25/0657 (2013.01); H01L 25/074 (2013.01); H01L 25/117 (2013.01);
Abstract

Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.


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