The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Feb. 25, 2014
Kabushiki Kaisha Toshiba, Minato-ku, Tokyo, JP;
Osamu Takata, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
An aspect of the present embodiment, there is provided a semiconductor device includes a high-voltage element, the high-voltage element including a substrate, a first semiconductor region with a first conductive type on the substrate, an insulating isolation film on the substrate, a second semiconductor region with a second conductive type, the second semiconductor region being provided between the first semiconductor region and the insulating isolation film, a drain region with the second conductive type provided on a surface of the second semiconductor region, an impurity concentration of the drain region being higher than an impurity concentration of the second semiconductor region, a source region with the second conductive type provided on a surface of the first semiconductor, the source region being separated from the drain region, a floating drain region with the second conductive type provided on the surface of the first semiconductor region between the second semiconductor region and the source region, a first gate electrode above the first semiconductor region between the drain region and the floating drain region, a second gate electrode above the first semiconductor region between the source region and the floating drain region, a gate insulator provided between the first gate electrode and the surface of the first semiconductor region, the first gate electrode and the surface of the second semiconductor region, and the second gate electrode and the surface of the first semiconductor region, a portion of the second semiconductor region being placed under the first gate electrode through the gate insulator to be overlapped with the first gate electrode, a drain electrode on the drain region, and a source electrode on the source region.