The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Dec. 27, 2005
Applicants:

Young Seok Choi, Daejeon, KR;

Hong Woo Yu, Gumi-si, KR;

Ki Sul Cho, Gumi-si, KR;

Jae Ow Lee, Ahndong-si, KR;

BO Kyoung Jung, Jeonju-si, KR;

Inventors:

Young Seok Choi, Daejeon, KR;

Hong Woo Yu, Gumi-si, KR;

Ki Sul Cho, Gumi-si, KR;

Jae Ow Lee, Ahndong-si, KR;

Bo Kyoung Jung, Jeonju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); G02F 1/1345 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13458 (2013.01); G02F 1/136213 (2013.01); H01L 27/124 (2013.01); H01L 27/1288 (2013.01); H01L 27/1255 (2013.01);
Abstract

A TFT array substrate is provided. The TFT array substrate includes a gate electrode connected to a gate line; a source electrode connected to a data line, the data line crossing the gate line to define a pixel region; a drain electrode facing the source electrode with a channel interposed therebetween; a semiconductor layer forming the channel between the source electrode and the drain electrode; a channel passivation layer formed on the channel to protect the semiconductor layer; a pixel electrode disposed in the pixel region to contact with the drain electrode; a storage capacitor including the pixel electrode extending over the gate line to form a storage area on a gate insulating layer on which a semiconductor layer pattern and a metal layer pattern are stacked; a gate pad extending from the gate line; and a data pad connected to the data line.


Find Patent Forward Citations

Loading…