The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2015

Filed:

Apr. 01, 2013
Applicant:

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Inventors:

Tadayoshi Miyamoto, Osaka, JP;

Kazuatsu Ito, Osaka, JP;

Mitsunobu Miyamoto, Osaka, JP;

Yutaka Takamaru, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/12 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 29/41733 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01);
Abstract

This semiconductor device (A) includes: a gate electrode () formed on a substrate (); a gate insulating layer () formed on the gate electrode; an oxide layer () which is formed on the gate insulating layer and which includes a semiconductor region () and a conductor region (); source and drain electrodes () electrically connected to the semiconductor region; a protective layer () formed on the source and drain electrodes; and a transparent electrode () formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer () with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.


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