Solid-state imaging device with column circuitry includung a latch part comprising a plurality of logic gates and switch circuitry

Abstract

In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.