The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2015
Filed:
Sep. 18, 2013
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Inventors:
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 27/108 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 27/0629 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 27/10814 (2013.01); H01L 27/10876 (2013.01); H01L 21/76229 (2013.01);
Abstract
A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.