The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Jan. 03, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Se-Ho You, Seoul, KR;

Heeseok Lee, Yongin-si, KR;

Chiyoung Lee, Hwaseong-si, KR;

Yun-Hee Lee, Daejeon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/10 (2006.01); H05K 7/12 (2006.01); H05K 1/18 (2006.01); H05K 1/11 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H05K 1/183 (2013.01); H05K 1/11 (2013.01); H05K 1/18 (2013.01); H05K 1/181 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/107 (2013.01); H01L 2924/1515 (2013.01); H01L 2924/15311 (2013.01); H01L 23/13 (2013.01); H01L 23/49816 (2013.01);
Abstract

Provided is a package substrate and a semiconductor package. The package substrate includes a main body having an upper surface and a lower surface opposite to the upper surface, a plurality of external terminals attached to the lower surface, and a plurality of grooves formed in regions of the lower surface to which the plurality of external terminals is not attached. The semiconductor package includes a package substrate, a semiconductor chip mounted on the upper surface of the semiconductor substrate, and a board providing a region mounted with the package substrate and being mounted with a plurality of mounting elements which are vertically aligned with the plurality of grooves and are inserted into the plurality of grooves.


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