N-path interleaving analog-to-digital converter (adc) with background calibration

Abstract

A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s() is accepted having a first frequency f1 and a bandwidth (BW). A clock at frequency fs creates n sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. A first tone signal s() is generated at second frequency f2, outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating n digital sample signals per clock period 1/fs. The n digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information for a rotating pair of digital sample signals.