The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Sep. 26, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Katsuhiko Funatsu, Kanagawa, JP;

Tomoaki Uno, Kanagawa, JP;

Toru Ueguri, Kanagawa, JP;

Yasushi Takahashi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/495 (2013.01); H01L 21/56 (2013.01); H01L 24/34 (2013.01); H01L 24/97 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 23/49575 (2013.01); H01L 2224/73221 (2013.01); H01L 2924/13091 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 2224/45144 (2013.01); H01L 2924/30107 (2013.01); H01L 23/3107 (2013.01); H01L 21/565 (2013.01); H01L 2224/97 (2013.01);
Abstract

To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained.


Find Patent Forward Citations

Loading…