The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Jul. 11, 2011
Applicants:

Laurent Marechal, Grenoble, FR;

Yvon Imbs, Quaix en Chartreuse, FR;

Romain Coffy, Saint Martin le Vinoux, FR;

Inventors:

Laurent Marechal, Grenoble, FR;

Yvon Imbs, Quaix en Chartreuse, FR;

Romain Coffy, Saint Martin le Vinoux, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 29/40 (2006.01); H01L 23/12 (2006.01); H01L 23/053 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 25/16 (2006.01); H01L 23/538 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 23/5383 (2013.01); H01L 23/5389 (2013.01); H01L 24/18 (2013.01); H01L 24/82 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 2224/18 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01058 (2013.01); H01L 2924/15311 (2013.01); H05K 1/185 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10674 (2013.01); H05K 2203/1469 (2013.01); H01L 2924/01033 (2013.01); H01L 23/642 (2013.01); H01L 25/16 (2013.01);
Abstract

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.


Find Patent Forward Citations

Loading…