The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Oct. 08, 2014
Applicant:

Robert N. Rountree, Cotopaxi, CO (US);

Inventor:

Robert N. Rountree, Cotopaxi, CO (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/73 (2006.01); H01L 21/331 (2006.01); H01L 29/735 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/735 (2013.01); H01L 27/0262 (2013.01); H01L 29/7302 (2013.01);
Abstract

A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal () and a second terminal (). A first lightly doped region () having a first conductivity type (N−) is formed on a second lightly doped region () having a second conductivity type (P−). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region () having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region. A first transistor () having a control terminal and having a first current path terminal coupled to the third heavily doped region and a second current path terminal coupled to the second terminal is arranged to control a holding voltage of the circuit.


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