The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Aug. 02, 2011
Applicant:

Nathan Bluzer, Rockville, MD (US);

Inventor:

Nathan Bluzer, Rockville, MD (US);

Assignee:

Northrop Grumman Systems Corporation, Falls Church, VA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/04 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/04 (2013.01); H01L 27/0251 (2013.01);
Abstract

A high sensitivity, high speed, and low noise, semiconductor non-destructive read-out (NDRO) device () for the conversion of a generated signal charge () into an output voltage having provisions for charge integration, charge transfer, and nondestructive charge read-out without kTC reset noise. The read-out device () includes charge sensing potential wells (), a MOSFET having a gate (), a source (), and a drain (), a feedback amplifier (), a current generator (), a reset gate (), a reset drain (), a multiplexer gate (), and a pair of adjacent CCD transfer gates (and). CMOS detector pixels with this NDRO form a compact structure for integrating generated charge, and high sensitivity readout, without kTC reset noise. The NDRO in CCD devices provides a fast sensitive charge to voltage transducer without kTC reset noise. Connecting several NDRO stages in series () provides multiple readout of a pixel to further improve sensitivity and performance of charge to voltage transduction.


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