The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Dec. 02, 2013
Applicant:

Palo Alto Research Center Incorporated, Palo Alto, CA (US);

Inventors:

Jurgen H. Daniel, San Francisco, CA (US);

Ana Claudia Arias, San Carlos, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/208 (2006.01); H01L 21/368 (2006.01); H01L 21/02 (2006.01); H01L 51/00 (2006.01); H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02288 (2013.01); H01L 21/368 (2013.01); H01L 29/78684 (2013.01); H01L 29/7869 (2013.01); H01L 51/0004 (2013.01); H01L 21/02488 (2013.01); H01L 21/02628 (2013.01); H01L 29/66772 (2013.01); H01L 29/66742 (2013.01); H01L 27/1292 (2013.01);
Abstract

A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor.


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