The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

Jul. 14, 2010
Applicants:

Paul A. Nygaard, Carlsbad, CA (US);

Stuart B. Molin, Carlsbad, CA (US);

Michael A. Stuber, Carlsbad, CA (US);

Inventors:

Paul A. Nygaard, Carlsbad, CA (US);

Stuart B. Molin, Carlsbad, CA (US);

Michael A. Stuber, Carlsbad, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/12 (2006.01); H01L 21/78 (2006.01); H01L 21/84 (2006.01); H01L 23/36 (2006.01); H01L 23/367 (2006.01); H01L 29/786 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76256 (2013.01); H01L 21/78 (2013.01); H01L 21/84 (2013.01); H01L 23/36 (2013.01); H01L 23/3677 (2013.01); H01L 27/1203 (2013.01); H01L 29/78603 (2013.01); H01L 29/78606 (2013.01); H01L 2924/3011 (2013.01); H01L 2224/03002 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/94 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/6835 (2013.01); H01L 2221/68377 (2013.01); H01L 2224/0345 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/131 (2013.01); H01L 2224/94 (2013.01); H01L 2224/11002 (2013.01); H01L 2924/1305 (2013.01);
Abstract

Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.


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