The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 2015

Filed:

May. 02, 2014
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, JP;

Inventor:

Kenji Nishikawa, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/66 (2006.01); H01L 23/495 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 23/49503 (2013.01); H01L 23/49575 (2013.01); H01L 23/544 (2013.01); H01L 24/48 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/83121 (2013.01); H01L 2224/8385 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/07802 (2013.01); H01L 24/32 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01033 (2013.01); H01L 23/495 (2013.01); H01L 2224/85 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.


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