The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Mar. 13, 2013
Applicant:
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Inventors:
Jung-kuk Lee, Gyeonggi-do, KR;
Sang-seok Kang, Gyeonggi-do, KR;
Woo-seop Kim, Seoul, KR;
Hyun-soo Kim, Gyeonggi-do, KR;
Assignee:
Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/08 (2006.01); G11C 29/56 (2006.01); G11C 29/14 (2006.01); G11C 7/22 (2006.01); G11C 11/4096 (2006.01); G11C 5/04 (2006.01); G11C 11/40 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/08 (2013.01); G11C 29/14 (2013.01); G11C 7/22 (2013.01); G11C 11/4096 (2013.01); G11C 5/04 (2013.01); G11C 11/40 (2013.01); G11C 29/56 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/0407 (2013.01);
Abstract
A memory module includes a first rank, a second rank and a test control unit. The first rank includes a plurality of semiconductor memory devices configured to operate in response to a first chip selection signal. The second rank includes a plurality of semiconductor memory devices configured to operate in response to a second chip selection signal. The test control unit is configured to simultaneously enable the first and second chip selection signals to test the first and second ranks in a test mode.