The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Nov. 15, 2012
Applicant:

D-wave Systems Inc., Burnaby, CA;

Inventors:

William Macready, Vancouver, CA;

Geordie Rose, Vancouver, CA;

Thomas Mahon, Vancouver, CA;

Peter Love, Haverford, PA (US);

Marshall Drew-Brook, Vancouver, CA;

Assignee:

D-Wave Systems Inc., Burnaby, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06G 7/32 (2006.01); G06F 17/00 (2006.01); G06N 5/00 (2006.01); G06F 17/10 (2006.01); G06F 17/11 (2006.01); G06N 99/00 (2010.01); B82Y 10/00 (2011.01);
U.S. Cl.
CPC ...
G06F 17/10 (2013.01); G06F 17/11 (2013.01); G06N 99/002 (2013.01); B82Y 10/00 (2013.01);
Abstract

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.


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