The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Nov. 18, 2011
Mauro Rossi, Gemona del Friuli, IT;
Giampietro Tecchiolli, Trento, IT;
Pierfrancesco Zuccato, Udine, IT;
Mauro Rossi, Gemona del Friuli, IT;
Giampietro Tecchiolli, Trento, IT;
Pierfrancesco Zuccato, Udine, IT;
Eurotech SpA, Amaro, IT;
Abstract
A network architecture is used for the communication between elementary calculus units or nodes of a supercomputer to execute a super-calculus processing application, partitionable and scalable at the level of calculus power in the range of PetaFLOPS. The supercomputer comprises a plurality of modular structures, each of which comprises a plurality of elementary calculus units or nodes defined by node cards a backplane, a root card, and a node communication network of the switched fabric fat tree type; ii) a synchronization architecture comprising a plurality of distinct node communication networks, configured for the communication of specific synchronization information different from network to network and with different characteristics; iii) a re-configurable Programmable Network Processor that implements the nodes both of the n-toroidal network and those of the synchronization networks. The node communication networks of the n-toroidal type and of the switched fabric fat tree type can be used alternately or simultaneously for the transmission between the calculus nodes of the same type of data and information also in a configuration of system partitions in order to achieve the desired interconnection topology of the nodes.