The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Apr. 09, 2012
Applicants:

Bon-yong Koo, Cheonan-si, KR;

Beom Jun Kim, Seoul, KR;

Ho Kyoon Kwon, Seoul, KR;

Inventors:

Bon-Yong Koo, Cheonan-si, KR;

Beom Jun Kim, Seoul, KR;

Ho Kyoon Kwon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/28 (2006.01); G11C 19/00 (2006.01);
U.S. Cl.
CPC ...
G09G 3/36 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0209 (2013.01); G11C 19/28 (2013.01);
Abstract

The present invention divides a wire supplying a scan start signal to a gate driver into two wires, so as to avoid overlapping a clock signal line. In this way the clock signal is not delayed by interference, and a gate driving margin may continue uninterrupted, thereby uniformly outputting a gate-on voltage. In particular, if the clock signal line is connected to all stages in the gate driver and the clock signal line overlaps the scan start signal line, unsightly horizontal bands appear on the image and the parallel gate lines generate a very large parasitic capacitance. In contrast, the gate drivers in the present disclosure comprise clock signal lines which do not overlap the scan start signal lines. As benefits, interference resulting in horizontal banding is minimized and the power consumption may be reduced by about 10%.


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