The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Nov. 08, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Ramanand Venkata, Fremont, CA (US);

Ryan Fung, Mississauga, CA (US);

Ketan H. Zaveri, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01);
Abstract

An integrated circuit includes a first vertical clock bus and a first interface circuit coupled to provide first global clock signals to the first vertical clock bus. The first interface circuit is coupled to a first external terminal of the integrated circuit. The integrated circuit also includes a second vertical clock bus and a second interface circuit coupled to provide second global clock signals to the second vertical clock bus. The second interface circuit is coupled to a second external terminal of the integrated circuit. A third horizontal clock bus is coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit.


Find Patent Forward Citations

Loading…