The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 2015

Filed:

Apr. 06, 2012
Applicants:

Valeria Puglisi, Catania, IT;

Corinna Altamore, Siracusa, IT;

Giovanni Abagnale, Catania, IT;

Inventors:

Valeria Puglisi, Catania, IT;

Corinna Altamore, Siracusa, IT;

Giovanni Abagnale, Catania, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/336 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 29/42376 (2013.01); H01L 29/2003 (2013.01); H01L 29/66462 (2013.01); H01L 29/4236 (2013.01);
Abstract

A method for manufacturing a HEMT transistor includes: realizing an undoped epitaxial layer on a substrate; realizing a barrier epitaxial layer on the undoped epitaxial layer so as to form a heterojunction; realizing source and drain structures, separated from one other, on the barrier epitaxial layer; depositing an insulating layer on the barrier epitaxial layer and on the source and drain structures; and photolithographic defining the insulating layer, defining first and second insulating portions in correspondence of the source and drain structures, respectively, and exposing a portion of the barrier epitaxial layer. The method further comprises: forming first and second spacers lying at the corners of the first and second insulating portions; and depositing a gate metal structure at least partially covering said first and second insulating portions, and said first and second spacers, said gate metal structure being a field plate of the HEMT transistor.


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