The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Jan. 22, 2007
Ashay Chitnis, Santa Barbara, CA (US);
James Ibbetson, Santa Barbara, CA (US);
Arpan Chakraborty, Goleta, CA (US);
Eric J. Tarsa, Goleta, CA (US);
Bernd Keller, Santa Barbara, CA (US);
James Seruto, Orcutt, CA (US);
Yankun Fu, Raleigh, NC (US);
Ashay Chitnis, Santa Barbara, CA (US);
James Ibbetson, Santa Barbara, CA (US);
Arpan Chakraborty, Goleta, CA (US);
Eric J. Tarsa, Goleta, CA (US);
Bernd Keller, Santa Barbara, CA (US);
James Seruto, Orcutt, CA (US);
Yankun Fu, Raleigh, NC (US);
Cree, Inc., Goleta, CA (US);
Abstract
Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.