The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2015
Filed:
Nov. 01, 2013
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Abhijeet Paul, Albany, NY (US);
Ajey Poovannummoottil Jacob, Albany, NY (US);
Min-hwa Chi, Malta, NY (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/8232 (2006.01); H01L 29/423 (2006.01); H01L 27/088 (2006.01); H01L 27/105 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/02587 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/1054 (2013.01); H01L 21/8232 (2013.01); H01L 29/1079 (2013.01); H01L 27/105 (2013.01); H01L 21/845 (2013.01); H01L 29/0847 (2013.01); H01L 29/42392 (2013.01); H01L 27/0886 (2013.01);
Abstract
Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods involve forming such alternating layers of different semiconductor materials in a cavity formed above the substrate fin and thereafter forming a gate structure around the fin using gate first or gate last techniques.