The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Aug. 28, 2012
Applicants:

Vincent Debout, La Ciotat, FR;

Frank Lhermet, Roquevaire, FR;

Yann Yves René Loisel, La Ciotat, FR;

Grégory Rome, Aix en Provence, FR;

Christophe Tremlet, Aubagne, FR;

Inventors:

Vincent Debout, La Ciotat, FR;

Frank Lhermet, Roquevaire, FR;

Yann Yves René Loisel, La Ciotat, FR;

Grégory Rome, Aix en Provence, FR;

Christophe Tremlet, Aubagne, FR;

Assignee:

Maxim Integrated Products, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/72 (2013.01); G06F 12/14 (2006.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 21/72 (2013.01); G06F 12/1408 (2013.01); G06F 21/79 (2013.01);
Abstract

The present invention relates to key management in a secure microcontroller, and more particularly, to systems, devices and methods of automatically and transparently employing logic or physical address based keys that may also be transferred using dedicated buses. A cryptographic engine translates a logic address to at least one physical address, and processes a corresponding data word based on at least one target key. The target key is selected from a plurality of keys based on the logic or physical address. A universal memory controller stores each processed data word in the corresponding physical address within a memory. Each key is associated with a memory region within the memory, and therefore, the logic or physical address associated with a memory region may be used to automatically identify the corresponding target key. A dedicated secure link may be used to transport key request commands and the plurality of keys.


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