The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Dec. 14, 2011
Applicants:

Yuki Sakashita, Yokohama, JP;

Shintaro Kudo, Yokohama, JP;

Yusuke Nonaka, Sagamihara, JP;

Inventors:

Yuki Sakashita, Yokohama, JP;

Shintaro Kudo, Yokohama, JP;

Yusuke Nonaka, Sagamihara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0658 (2013.01); G06F 3/0689 (2013.01); G06F 3/0626 (2013.01); G06F 3/067 (2013.01);
Abstract

According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided. Further, each duplication information area is provided with a double master information area capable of referring to a first memory and a second memory and a single master information area capable of referring only to either the first memory or the second memory, and the accesses thereto are performed based on the attribute information.


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