The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Aug. 19, 2011
Applicants:

Ravindraraj Ramaraju, Round Rock, TX (US);

David R. Bearden, Austin, TX (US);

Prashant U. Kenkare, Austin, TX (US);

Jogendra C. Sarker, Austin, TX (US);

Inventors:

Ravindraraj Ramaraju, Round Rock, TX (US);

David R. Bearden, Austin, TX (US);

Prashant U. Kenkare, Austin, TX (US);

Jogendra C. Sarker, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/355 (2006.01); G06F 9/38 (2006.01); G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1027 (2013.01); G06F 9/355 (2013.01); G06F 9/3832 (2013.01);
Abstract

A method and data processing system for accessing an entry in a memory array by placing a tag memory unit () in parallel with an operand adder circuit () to enable tag lookup and generation of speculative way hit/miss information () directly from the operands () without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands () are applied with a carry-out value (Cout) to a content-addressable memory array () to generate two speculative hit/miss signals. A sum value (EA) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output ().


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