The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Sep. 16, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Nicola Da Dalt, Sattendorf, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/033 (2006.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01); H03L 7/197 (2006.01); H03L 7/091 (2006.01);
U.S. Cl.
CPC ...
H03L 7/093 (2013.01); H03L 7/1972 (2013.01); H03L 7/1974 (2013.01); H03L 7/091 (2013.01);
Abstract

This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.


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