The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2015
Filed:
May. 07, 2013
Applicant:
Ps4 Luxco S.a.r.l., Luxembourg, LU;
Inventors:
Yasuhiro Matsumoto, Tokyo, JP;
Noriaki Mochida, Tokyo, JP;
Takeshi Ohgami, Tokyo, JP;
Daiki Izawa, Tokyo, JP;
Assignee:
PS4 Luxco S.A.R.L., Luxembourg, LU;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/4099 (2006.01); G11C 7/18 (2006.01); G11C 29/00 (2006.01); G11C 29/06 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4094 (2013.01); G11C 11/4097 (2013.01); G11C 11/4099 (2013.01); G11C 7/18 (2013.01); G11C 29/006 (2013.01); G11C 29/06 (2013.01); G11C 2029/1204 (2013.01);
Abstract
A semiconductor device having hierarchical bit lines is disclosed, which comprises: a first global bit line; first and second local bit lines coupled in common to the first global bit line; first and second power lines; a first transistor coupled between the first local bit line and the first power line; a second transistor coupled between the second local bit line and the second power line; a third transistor coupled between the first and second power lines.