The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

May. 23, 2011
Applicants:

Yang Han, Sunnyvale, CA (US);

Zongwang LI, San Jose, CA (US);

Shaohua Yang, San Jose, CA (US);

Wu Chang, Santa Clara, CA (US);

Inventors:

Yang Han, Sunnyvale, CA (US);

Zongwang Li, San Jose, CA (US);

Shaohua Yang, San Jose, CA (US);

Wu Chang, Santa Clara, CA (US);

Assignee:

LSI Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/012 (2006.01); G11B 5/09 (2006.01); G11B 20/18 (2006.01); G11B 20/12 (2006.01);
U.S. Cl.
CPC ...
G11B 5/012 (2013.01); G11B 2020/1222 (2013.01); G11B 2020/1288 (2013.01); G11B 5/09 (2013.01); G11B 2220/2516 (2013.01); G11B 20/1217 (2013.01); G11B 20/1833 (2013.01); G11B 20/1866 (2013.01); G11B 2020/1267 (2013.01);
Abstract

Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output.


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