The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2015
Filed:
Jun. 12, 2012
Applicant:
Katsunao Kanari, Kawasaki, JP;
Inventor:
Katsunao Kanari, Kawasaki, JP;
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/096 (2006.01); H03K 3/356 (2006.01); H03K 3/012 (2006.01);
U.S. Cl.
CPC ...
H03K 3/356147 (2013.01); H03K 3/012 (2013.01);
Abstract
A latch circuit includes a latch unit and a clock propagation suppressing unit. The latch circuit holds and outputs input data of 0 or 1. The clock propagation suppressing unit compares the input data input to the latch unit with output data output from the latch unit. When it is detected that the input data matches the output data at 0, or that the input data matches the output data at 1, an externally input clock signal is prevented from propagating to the latch unit.
Kanari, Katsunao. (2015). Latch circuit and clock control circuit (U.S. Patent No. 9018981). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9018981
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile