The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Dec. 31, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Anton Prueckl, Schierling, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 25/16 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 24/24 (2013.01); H01L 24/95 (2013.01); H01L 23/49575 (2013.01); H01L 23/49562 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/24246 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/92244 (2013.01); H01L 25/16 (2013.01);
Abstract

A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.


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