The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

May. 30, 2014
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Makoto Wada, Yokohama, JP;

Kazuyuki Higashi, Yokohama, JP;

Naofumi Nakamura, Setagaya-ku, JP;

Tsuneo Uenaka, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76808 (2013.01); H01L 21/76816 (2013.01); H01L 23/5226 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11578 (2013.01); H01L 29/66825 (2013.01); H01L 29/66833 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); H01L 29/7926 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.


Find Patent Forward Citations

Loading…