The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Jul. 10, 2013
Applicant:

Excelitas Canada, Inc., Vaudreuil-Dorion, CA;

Inventors:

Xianzhu Zhang, Pointe-Claire, CA;

Jerry Deleon, Calamba, PH;

Arthur John Barlow, Alton, GB;

Assignee:

Excelitas Canada, Inc., Vaudreuil-Dorion, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 23/00 (2006.01); H01L 33/48 (2010.01); H01L 33/64 (2010.01); H01S 5/022 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/50 (2013.01); H01L 33/486 (2013.01); H01L 33/64 (2013.01); H01S 5/02228 (2013.01); H01S 5/02236 (2013.01); H01S 5/02252 (2013.01); H01S 5/02276 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/3011 (2013.01); H01L 24/97 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/48472 (2013.01); H01L 2924/00014 (2013.01); H01L 23/3121 (2013.01); H01L 21/56 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/1461 (2013.01);
Abstract

Embodiments of a laminate leadless carrier package are presented. The package includes an optoelectronic chip, a substrate supporting the optoelectronic chip, a plurality of conductive slotted vias, a wire bond pad disposed on the top surface of the substrate, a wire bond coupled to the optoelectronic chip and the wire bond pad and an encapsulation covering the optoelectronic chip, the wire bond, and at least a portion of the top surface of the substrate. The slotted vias provide electrical connections between the top conductive layer and the bottom conductive layer. The substrate includes a plurality of conductive and dielectric layers laminated together including a bottom conductive layer, a top conductive layer, and a dielectric layer between the top and bottom conductive layers. The encapsulation is a molding compound, and the molding compound is pulled back from at least one of the slotted vias.


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