The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 28, 2015

Filed:

Aug. 27, 2010
Applicants:

Young Seok Choi, Gumi-si, KR;

Hong Woo Yu, Gumi-si, KR;

Ki Sul Cho, Gumi-si, KR;

Jae Ow Lee, Ahndong-si, KR;

BO Kyoung Jung, Jeonju-si, KR;

Inventors:

Young Seok Choi, Gumi-si, KR;

Hong Woo Yu, Gumi-si, KR;

Ki Sul Cho, Gumi-si, KR;

Jae Ow Lee, Ahndong-si, KR;

Bo Kyoung Jung, Jeonju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); G02F 1/1345 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G02F 1/13458 (2013.01); H01L 27/124 (2013.01); H01L 27/1288 (2013.01); H01L 27/1255 (2013.01); H01L 27/1214 (2013.01); G02F 2001/136236 (2013.01);
Abstract

A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line.


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