The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2015
Filed:
Oct. 24, 2013
Oracle International Corporation, Redwood City, CA (US);
Vamshi Pampati, San Jose, CA (US);
Tony Hoang, Mountain House, CA (US);
Mini Nanua, Cedar Park, TX (US);
Oracle International Corporation, Redwood City, CA (US);
Abstract
Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design. Thus, by combining the hierarchical extraction with an intelligent connectivity technique, an electromigration analysis of a VLSI microelectronic design may be accomplished within the limitations of the analysis tools that is more accurate than previous electromigration analysis techniques.