The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Jun. 18, 2013
Applicant:

Round Rock Research, Llc, Parsippany, NJ (US);

Inventors:

Mehdi Asnaashari, Danville, CA (US);

Ronald Yamada, Santa Clara, CA (US);

Siamack Nemazie, Los Altos Hills, CA (US);

Jui-Yao Yang, San Jose, CA (US);

Assignee:

Round Rock Research, LLC, Parsippany, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); G06F 13/28 (2006.01); G06F 21/64 (2013.01); H03M 13/09 (2006.01); G11C 29/04 (2006.01); H03M 13/13 (2006.01);
U.S. Cl.
CPC ...
H03M 13/29 (2013.01); G06F 11/10 (2013.01); G06F 13/28 (2013.01); G06F 21/64 (2013.01); G11C 2029/0411 (2013.01); H03M 13/09 (2013.01); H03M 13/13 (2013.01);
Abstract

The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.


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