The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Dec. 03, 2012
Applicants:

Ramsundar Janakiraman, Sunnyvale, CA (US);

Prasad Palkar, Sunnyvale, CA (US);

Brijesh Nambiar, Santa Clara, CA (US);

Sridhar Kamsetty, San Jose, CA (US);

Vijayaraghavan Doraiswami, Santa Clara, CA (US);

Inventors:

Ramsundar Janakiraman, Sunnyvale, CA (US);

Prasad Palkar, Sunnyvale, CA (US);

Brijesh Nambiar, Santa Clara, CA (US);

Sridhar Kamsetty, San Jose, CA (US);

Vijayaraghavan Doraiswami, Santa Clara, CA (US);

Assignee:

Aruba Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/52 (2006.01); H04L 12/54 (2013.01);
U.S. Cl.
CPC ...
G06F 9/526 (2013.01); H04L 12/56 (2013.01);
Abstract

The present disclosure discloses a method and network device for achieving enhanced performance with multiple CPU cores in a network device having a symmetric multiprocessing architecture. The disclosed method allows for storing, by each central processing unit (CPU) core, a non-atomic data structure, which is specific to each networking CPU core, in a memory shared by the plurality of CPU cores. Also, the memory is not associated with any locking mechanism. In response to a data packet is received by a particular CPU core, the disclosed system will update a value of the non-atomic data structure corresponding to the particular CPU core. The data structure may be a counter or a fragment table. Further, a dedicated CPU core is allocated to process only data packets received from other CPU cores, and is responsible for dynamically responding to queries receives from a control plane process.


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