The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2015
Filed:
May. 05, 2010
Tim Tuan, San Jose, CA (US);
Daniel Chung, San Ramon, CA (US);
Ronald Cline, Tijeras, NM (US);
Andy Debaets, Cupertino, CA (US);
Matthew H. Klein, Redwood City, CA (US);
Tim Tuan, San Jose, CA (US);
Daniel Chung, San Ramon, CA (US);
Ronald Cline, Tijeras, NM (US);
Andy DeBaets, Cupertino, CA (US);
Matthew H. Klein, Redwood City, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay. A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined. The circuit design is synthesized such that the synthesized design includes the voltage scaling value. The synthesized design specifies setting an operating voltage to a value of a startup voltage value scaled by the voltage scaling value.