The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Aug. 30, 2013
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Jos Verlinden, Wachtendonk, DE;

Remco Cornelis Herman van de Beek, Eindhoven, NL;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H04L 7/0079 (2013.01);
Abstract

Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.


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Verlinden, Jos. (2015). Clock synchronizer for aligning remote devices (U.S. Patent No. 9014323). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9014323

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