The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Sep. 15, 2011
Applicants:

Shohei Katsuta, Osaka, JP;

Tsuyoshi Kamada, Osaka, JP;

Seiji Ohhashi, Osaka, JP;

Inventors:

Shohei Katsuta, Osaka, JP;

Tsuyoshi Kamada, Osaka, JP;

Seiji Ohhashi, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G03B 21/00 (2006.01); H04N 13/00 (2006.01); H04N 13/04 (2006.01); G09G 3/00 (2006.01); G02B 27/26 (2006.01); G02F 1/13363 (2006.01);
U.S. Cl.
CPC ...
G09G 3/001 (2013.01); G09G 3/003 (2013.01); G09G 3/3677 (2013.01); H04N 13/0434 (2013.01); G02B 27/26 (2013.01); G02F 2001/133631 (2013.01);
Abstract

A liquid crystal display device () includes a liquid crystal panel having a plurality of pixels disposed in a matrix form, and a patterned retarder having retarder plates (RR) and retarder plates (RL) formed at positions corresponding to odd-numbered rows and even-numbered rows, respectively, of the liquid crystal panel. Among sub pixels disposed in the pixels positioned in the n-th row, a sub pixel electrode of a boundary-proximity sub pixel, which is positioned closest to a boundary between the associated retarder plate (RR) and the associated retarder plate (RL), is connected to an auxiliary bus line via a transistor having a gate electrode connected to a gate bus line in the (n−1)-th or prior row. In the second display mode, gate signals are sequentially supplied to the gate bus lines in order from the first to the N-th rows, and, in the first display mode, gate signals are sequentially supplied to the gate bus lines in order from the N-th to the first rows.


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