The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Dec. 09, 2013
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Heat Bit Park, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G11C 7/20 (2006.01); H01L 25/065 (2006.01); G11C 7/22 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G11C 7/222 (2013.01); G06F 13/4068 (2013.01); G06F 13/00 (2013.01);
Abstract

Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip ID signal generation unit configured to generate a chip ID signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip ID signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip ID signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal.


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