The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Feb. 25, 2013
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Nobuyuki Suzuki, Oita, JP;

Satoshi Suzuki, Fujisawa, JP;

Masanobu Ohmura, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/82 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 27/092 (2013.01); H01L 21/823814 (2013.01); H01L 21/82385 (2013.01); H01L 21/823857 (2013.01); H01L 27/0922 (2013.01);
Abstract

A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the DMOS transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the NMOS transistor and the PMOS transistor, and forming the second impurity region and the other of the NMOS transistor and the PMOS transistor.


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