The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9012312 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 21, 2015

Filed:

Mar. 04, 2014
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventor:

Tomoyuki Furuhata, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01); H01L 21/265 (2006.01); H01L 21/761 (2006.01); H01L 21/74 (2006.01); H01L 21/8234 (2006.01); H01L 29/732 (2006.01);
U.S. Cl.
CPC ...
H01L 21/265 (2013.01); H01L 21/761 (2013.01); H01L 21/74 (2013.01); H01L 21/823481 (2013.01); H01L 29/7322 (2013.01);
Abstract

A semiconductor device manufacturing method includes (a) forming a buried diffusion layer of a first conductivity type in a semiconductor substrate of a second conductivity type, (b) forming a first impurity region by implanting an impurity of the first conductivity type, (c) diffusing the buried diffusion layer and the first impurity region to an extent that the buried diffusion layer and the first impurity region are not connected by performing a first thermal process on the semiconductor substrate, (d) forming a second impurity region by implanting an impurity of the first conductivity type at a concentration higher than that of in step (b), and (e) diffusing the buried diffusion layer, the first impurity region, and the second impurity region by performing a second thermal process on the semiconductor substrate.


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