The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Apr. 11, 2013
Applicant:

Intersil Americas Llc, Milpitas, CA (US);

Inventors:

Jian Yin, San Jose, CA (US);

Nikhil Vishwanath Kelkar, Saratoga, CA (US);

Loyde Milton Carpenter, Jr., Palm Bay, FL (US);

Assignee:

Intersil Americas LLC, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49527 (2013.01); H01L 23/49531 (2013.01); H01L 23/49575 (2013.01); H01L 21/4832 (2013.01); H01L 24/32 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/12032 (2013.01);
Abstract

Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.


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