The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2015

Filed:

Sep. 28, 2011
Applicants:

Shinya Nakano, Tokyo, JP;

Yoshiaki Takeuchi, Tokyo, JP;

Michio Kondo, Tsukuba, JP;

Takuya Matsui, Tsukuba, JP;

Inventors:

Shinya Nakano, Tokyo, JP;

Yoshiaki Takeuchi, Tokyo, JP;

Michio Kondo, Tsukuba, JP;

Takuya Matsui, Tsukuba, JP;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/20 (2006.01); H01L 31/18 (2006.01); H01L 31/0376 (2006.01); H01L 31/0747 (2012.01);
U.S. Cl.
CPC ...
H01L 31/202 (2013.01); H01L 31/1804 (2013.01); H01L 31/03762 (2013.01); H01L 31/0747 (2013.01); Y02E 10/547 (2013.01);
Abstract

A process for producing a photovoltaic device that can improve the power generation characteristics of a solar cell having a heterojunction composed of a p-type crystalline Ge (substrate), an i-type amorphous silicon semiconductor layer, and an n-type amorphous silicon semiconductor layer. A process for producing a photovoltaic device () comprising a heterojunction cell () prepared by sequentially stacking an i-type amorphous silicon semiconductor layer () and an n-type amorphous silicon semiconductor layer () on top of a substrate (p-type crystalline Ge ()), the process comprising a PHexposure treatment stage of adjusting the temperature of the substrate (), from which a surface oxide film has been removed, to a prescribed temperature, and subsequently placing the substrate in a vacuum chamber and exposing the substrate to PH, an i-layer deposition stage of depositing the i-type amorphous silicon semiconductor layer () on the PH-exposed substrate, an n-layer deposition stage of depositing the n-type amorphous silicon semiconductor layer () on the i-type amorphous silicon semiconductor layer (), and an electrode formation stage of forming electrodes () on the surface of the n-type amorphous silicon semiconductor layer, and on the back surface of the substrate ().


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