The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 2015
Filed:
Dec. 20, 2013
Freescale Semiconductor, Inc., Austin, TX (US);
Puneet Sharma, Austin, TX (US);
Chi-Min Yuan, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.